1. Technical Field
The present invention relates generally to the data processing field, and more particularly, to a FIFO sub-system for disk formatters and to a method for controlling the movement of data in a data processing system.
2. Description of the Related Art
Disk controllers are used to control the movement of data based on a request from an external system. A disk formatter is a submodule of a disk controller. Traditional disk formatters include a FIFO (First In-First Out) sub-system (sometimes referred to herein as a “FIFO”) built from a single RAM (Random Access Memory) and having a first interface to larger memory device, such as a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory), with an associated buffer controller to interface to the larger memory device, and a second interface to a Read/Write (R/W) channel device. Typically, the first interface's data path width is some multiple of the second interface's data path width. For example, the first interface can be 32-bits and the second interface can be 8-bits. Translation of the data path width in the FIFO sub-system is relatively straightforward and all counters are usually byte based. The interface to a DDR SDRAM controller, for example, transfers data on each clock that is as wide as the first interface. In addition, sector sizes are usually a multiple of the first and second interfaces.
Although the interfaces in this traditional disk controller FIFO are relatively easy to design, the FIFO does not provide satisfactory solutions to problems that may be encountered with respect to data width conversion, sector sizes that are not a multiple of the first interface, or a first interface which does not transfer its entire width on a given clock. In addition, this traditional FIFO does not provide an in-line ECC (Error Correcting Code) correction capability that is desirable in many applications.
Numerous FIFO sub-systems have been developed in an effort to overcome some of the inadequacies of traditional disk formatter FIFOs. For example, one known FIFO sub-system design includes two interfaces and provides error correction by having the ECC module work directly with the buffer controller arbiter to perform error correction during read operations. In this approach, buffer accesses must be performed in real time since the ECC module is part of a pipeline that needs to complete each set of buffer accesses within a sector time or less. Accordingly, this approach requires additional buffer bandwidth which will decrease the amount of buffer bandwidth available for other channels in the system.
Other known FIFO sub-systems include a third interface to provide in-line ECC correction. For example, one known FIFO sub-system having three interfaces utilizes three RAMs that alternate interfacing to the three interfaces during a data transfer operation. Each RAM is sized to hold one sector and implements a pipeline so that the three interfaces can work in parallel. For example, as the buffer controller receives data from a first sector from one RAM, a second RAM interfaces to the ECC to correct a second sector, and the R/W channel transmits data for a third sector into a third RAM. Each RAM rotates between the three interfaces so that each RAM can handle all of the transfer for a given sector. In one FIFO sub-system design, datapath width conversion is provided in the middle of the sub-system, while in another design, width conversion is performed at the first interface. These designs suffer from various disadvantages including restrictions in sector size, insufficient margins for latencies, increased complexity and increased size.
Another FIFO design having three interfaces utilizes a single three-port RAM with a different port of the RAM connected to each interface. Logic outside of the FIFO logic performs conversion between datapath widths. This design has the disadvantage of requiring a three-port RAM and requires solving problems encountered with respect to datapath width conversions in real time as the data is transferred with the R/W channel or the buffer controller.
In general, in known FIFO sub-systems that include an ECC capability, the ECC can negatively affect the overall bandwidth of the buffer. In current data processing systems, R/W data channel interfaces are increasing beyond 8-bits and many devices use a 32-bit DDR SDRAM. Due to on-demand requirements on the host interface side of the buffer controller, it is especially important that the ECC does not affect overall buffer bandwidth.
There is, accordingly, a need for a FIFO sub-system for a disk formatter in a data processing system that provides ECC correction and data path conversion without affecting the bandwidth of the buffer.